Ruzica Jevtic - reportDuring the three months period of time, from 29 th of September 2004 until 20 th of December 2004, I have worked at the Department of Electronics, E.T.S.I Telecomunicacion, Universidad Politécnica de Madrid (UPM) in Madrid , Spain , as a part of a Tempus CARDS Joint European Project JEP 17028.
The aims of my work there were realization of my final degree project and also getting familiar with laboratory equipment and laboratory exercises realization at the Department of Electronics Engineering, Departamento de Ingeneria Electronica (DIE), of UPM.
The project I was working on, was about implementing CSR (Compressed Sparse Row) algorithm into FPGA (Field Programmable Gate Array) chips (details>>). This algorithm is one of the sparse matrix multiplication algorithms and is widely used for information retrieval. Experiments showed that it is more efficient in terms of storage space requirement and query processing timing over the other sparse matrix algorithms for information retrieval application.
I learned a lot about characteristics of Virtex II family of FPGA chips, since the aim of my project was to implement this algorithm into Virtex II XC2V6000 family. The system was designed in a hardware description language – RTL VHDL. It was simulated using VHDL libraries with Model Technologies' ModelSim and synthesized using Xilinx's Design Manager. In order to use important feature of FPGA chips, reconfigurability, I wrote a VHDL code which can be easily transformed and used for another information retrieval algorithm, in this case CSC (Compressed Sparse Column). I also had to experiment with relationships between the area and timing constraints which helped me to exploit the parallelism of matrix multiplication implemented in FPGA chips. I defended this project as my B. Sc. graduation thesis when I came back from Madrid, at Faculty of Electrical Engineering, Belgrade University, Serbia and Montenegro.
As for laboratory exercise overview, I participated in exercising process in the Electronics Laboratory for third year students at E.T.S.I Telecomunicacion. Main idea of this course was for students to apply in practice their theoretical knowledge they gained in electronic courses in second year. They were supposed to design one audio system which consisted of two parts: analog and digital. They were given specifications of the system, but were free to use electronic components they chose as well as technology and a way of realization. I saw that this kind of laboratory exercises induced students to explore both fields of electronic, analog and digital and at the same time learn more about electrical engineering in an interesting way. The whole documentation about laboratory is given as an addition to the report about my final degree project (details>>).
During Tempus CARDS Joint European Project JEP 17028, that I have participated in, I have had an opportunity to experience the research and design process dealing with digital circuits. It helped me apply a broad theoretical knowledge I gained at my Faculty and at the same time achieve valuable practical experience. I also saw some new ways of doing laboratory exercises and could compare them with ones we have in Belgrade, since during my fifth year of studying I worked as a lab assistant at Department of Electronics, Faculty of Electrical Engineering, Belgrade, Serbia and Montenegro.
Ružica Jevtic